1. Technical Field
The disclosed subject matter relates to an optical network having one or more photonic switching nodes.
2. Background Information
Contemporary high performance computing (HPC) systems typically use the distributed shared memory (DSM) paradigm, wherein the entire memory is logically shared among all the processors but may be physically implemented using memory modules distributed across many computing nodes. This approach simplifies programming, provides portability of software, and exhibits improved scalability over traditional shared memory systems. Large scale DSM systems, however, suffer from a fundamental communication problem that significantly affects scalability: increased latency of remote memory accesses. The remote access latency problem is becoming critically more pronounced with faster processor speeds as each memory access consumes a correspondingly larger number of clock cycles.
Interconnection networks with low latency and high bandwidth have therefore become an important component in the design of HPC systems. Cutting-edge electronic transmission technologies, such as Hyper-transport and PCI-Express, as well as high performance cross-point switching fabrics are currently used to construct such networks. However, a performance gap is beginning to emerge between the processors, whose performance scales quickly according to Moore's law, and the interconnecting medium which fails to advance at a commensurate rate due to fundamental physical limitations. Dynamic power consumption, wiring density, and signal distortion are fundamental impediments to the scaling of electronic interconnection networks. Additionally, transmission of signals at high data rates (e.g., in excess of 1 Gb/s) over long electronic transmission lines (e.g., longer than 1 m) results in signal distortion which makes decoding these signals difficult or requires great amounts of power, large chip area, and high cost to ensure correct detection. Sophisticated signal processing techniques, such as pre-emphasis and equalization, can mitigate these effects to some extent, but they add to the overall latency and are expensive both in power and area. An alternative approach is to use relatively short transmission lines and an indirect topology such as a mesh or a torus, based on low-radix routers, but this approach leads to further increases in the overall latency as each packet has to traverse a larger number of hops.
Photonic interconnection networks are a potentially transformative technology with the capability to overcome these limitations and provide commensurate performance scaling. The enormous bandwidth of optical fibers, approximately 32 THz, facilitates the transmission of multiple data streams on a single fiber at very high data-rates using wavelength division multiplexing (WDM). The low loss in fibers, nearly zero for the distances relevant to interconnection networks, alleviates the need for regeneration and effectively removes the signal transmission limitation. The photonic medium also allows for bidirectional transmission and switching of high-rate data using optical switching elements completely transparent to the modulated data, a property known as bit-rate transparency. Semiconductor optical amplifiers (SOAs) are used in several experimental optical packet switching systems as on-off photonic gates, providing a substantial gain over a wide switching band, and sub-ns switching times.
Photonic technology presents, however, some fundamental design challenges specifically in its lack of efficient buffering and processing capabilities. Although some promising technologies such as photonic crystals are being investigated and may prove useful in constructing photonic memories and logic gates, they have failed to reach commercialization thus far. Optical buffers based on recirculating fiber delay lines have been demonstrated as have interferometeric optical logic gates but their dimensions and “bulkiness” prohibit them from becoming cost-effective solutions.
An impediment to the construction of photonic interconnection networks lies in the high cost and large footprints associated with using discrete optical elements such as lasers, modulators, switches and passive optics. Photonic integration, the fabrication of circuits implementing multiple photonic functions in a single package, is promising to eliminate these final barriers. Since the elements comprising the prohibitive cost of optical networks mainly lie in the assembly and packaging of very large systems, and a significant share of the power consumption rises from coupling losses between individually packaged devices, integration of large parts of the network on a single photonic integrated circuit (PIC) alleviates these factors. Monolithic Indium-Phosphide PICs containing 50 photonic functions have been reported in scientific literature and are now commercially available. Additionally, silicon-based optical and electro-optical components such as modulators, photodetectors, and waveguides, all compatible with standard (CMOS) processing techniques have recently become available, promising an unprecedented potential for low cost electronic-optical interfacing.
When photonic integration is harnessed to construct interconnection networks, however, buffering becomes very difficult. The optical packet typically occupies a fixed length of a waveguiding medium which is the product of the speed of light in the medium and the duration of the packet. The size of optical packets known in the art occupy a certain amount of space, such that it is difficult, if not impossible, to fit on an integrated circuit. For example, a typical 100-ns packet will occupy 20 meters of silica fiber or 6 meters of a semiconductor waveguide. Consequently, buffering optical packets within a PIC is not currently practical.
Accordingly, there is a need in the art to provide a scalable interconnection network based on photonic integration that offers a bufferless means of contention resolution.